1. Field of the Invention
The invention relates to a wiring structure and a semiconductor device including the wiring structure, and more particularly to a dual-damascene wiring structure and a semiconductor device including the dual-damascene wiring structure.
2. Description of the Related Art
In a conventional semiconductor device, a metal wire has been usually composed of aluminum or aluminum alloy. This is because aluminum and aluminum alloy can be readily patterned through the use of a photoresist mask and etching gas, since aluminum and aluminum alloy have a low resistivity.
In these days, with reduction in a size of a semiconductor device and increase in an operation rate of a semiconductor device, there is a need for a material of which a wiring is to be composed and which has a lower resistivity and a higher current density than aluminum and aluminum alloy. As a material meeting with such requirements, copper (Cu) draws much attention.
When a copper wiring is to be patterned, if a copper wiring is etched in the same manner as an aluminum wiring, copper is harmfully affected by etching gas and moisture, resulting in that corrosion occurs inside the copper wiring. Accordingly, unlike an aluminum wiring, it is not suitable to pattern a copper wiring through the use of a photoresist mask and etching gas.
As a method of patterning a copper wiring without occurrence of corrosion, there is known a damascene process. A damascene process is a process for forming a copper wiring on an underlying layer, including steps of forming a recess with an underlying layer, filling the recess with copper, and polishing the copper for removal of unnecessary portions of the copper.
When an upper wiring layer and a lower wiring layer are electrically connected to each other in a multi-wiring layer structure, a via-hole is formed throughout an interlayer insulating film sandwiched between the upper and lower wiring layers, and then, a via-conductor is formed by filling the via-hole with electrical conductor such as metal. The upper and lower wiring layers are electrically connected to each other through the thus formed via-conductor.
In this process, if the upper wiring layer and the via-conductor were formed in separate steps, a time necessary for fabricating a multi-layer wiring structure would be increased. Hence, a dual-damascene process is generally used in order to shorten the above-mentioned fabrication time. Herein, a dual-damascene process is a process including steps of filling both of a via-hole formed with an interlayer insulating film and a recess formed with an upper wiring layer with metal in a single common step, and polishing the metal such that the metal remains only in the via-hole and the recess, to thereby form a via-conductor.
In a dual-damascene process, a via-conductor is generally composed of copper, similarly to a damascene process.
It is known that a copper plating film has a lot of voids at a size of 10 nm or so. Such voids are agglomerated by migration, gather at a grain boundary, and develop into a larger void.
A plated copper has a grain larger than the same in a film formed by sputtering. As a result, grain having superior crystalline can be formed in plated copper. Such grain having superior crystalline is more likely to be formed in a wiring layer having a greater width. This is because crystalline is degraded by a sidewall of a wiring layer. As a result, a wiring layer having a small width often has inferior crystalline relative to a wiring layer having a great width. The inventors found out that such difference in crystalline presented the following facts by which voids were caused.
(a) Voids are more likely to be diffused in a wiring layer having a greater width than in a wiring layer having a smaller width, because of superiority in crystalline of a wiring layer having a greater width relative to the same of a wiring layer having a smaller width.
(b) Since a wiring layer having a greater width has superiority in crystalline relative to the same of a wiring layer having a smaller width, a wiring layer having a greater width has free energy smaller than that of a wiring layer having a smaller width.
(c) Since a wiring layer having a greater width has superiority in crystalline relative to the same of a wiring layer having a smaller width, grains a wiring layer having a smaller width are thermally instable than a wiring layer having a greater width with respect to surface energy.
Due to the above-mentioned three facts, there occurs a phenomenon in which a volume moves towards a wiring layer having a great width from a wiring layer having a small width in dependence on annealing and a size. This phenomenon is called agglomeration.
The inventors found out that it would be effective to restrict energy gradient in order to solve the agglomeration. Thus, the inventors present a solution to the problem that agglomeration occurs because a wiring layer is connected to a thin wiring or a small via-contact in dependence on an area or a volume of the wiring layer.
Copper tends to be agglomerated, if annealed at a high temperature. For instance, if a thin copper film were annealed at a high temperature, the thin copper film would be agglomerated into a small circular piece. A thinner copper film is more likely to be agglomerated. A thin copper film having been agglomerated is no longer able to be used as a material of which a copper wiring is composed. This is because, if a copper film were agglomerated, the copper film would contain void, and resultingly, would have wiring defects such as breakage.
Hereinbelow are explained examples of wiring defects observed in a copper wiring fabricated in accordance with a conventional dual-damascene process.
FIG. 1A is a cross-sectional view illustrating a first example of a multi-layered wiring structure composed of copper.
First, a recess is formed at a surface of a lower insulating layer 104, and then, a lower copper wiring layer 105 is formed in the recess.
The lower copper wiring layer 105 is formed as follows, for instance.
First, a barrier metal layer is deposited on an inner wall of the recess by sputtering. Then, the recess is filled with copper by electrolytic plating. Then, copper deposited on the lower insulating layer 104 is removed by chemical mechanical polishing (CMP). Thus, the lower copper wiring layer 105 is formed just in the recess.
After the formation of the lower copper wiring layer 105, a silicon nitride (SiN) layer 106, a silicon dioxide (SiO2) layer 107, a silicon nitride (SiN) layer 116 and a silicon dioxide (SiO2) layer 117 are formed as an interlayer insulating layer on the lower insulating layer 104 and the lower copper wiring layer 105.
Then, the interlayer insulating layer is formed with a via-hole 108. The thus formed via-hole 108 is filled with resist. Thereafter, the silicon nitride (SiN) layer 116 and the silicon dioxide (SiO2) layer 117 are removed in selected areas to thereby form a second recess in which an upper wiring layer is to be formed.
Then, while the second recess and the via-hole 108 are kept exposed, a via-conductor 109 and an upper wiring layer 110 are formed in a common step. For instance, a barrier metal layer is deposited on inner walls of the second recess and the via-hole 108 by sputtering, and then, a copper layer is formed over the barrier metal layer by electrolytic plating. Copper deposited on the silicon dioxide (SiO2) layer 117 is polished for removal.
Thus, there is formed a dual-damascene wiring comprised of the via-conductor 109 and the upper wiring layer 110.
Then, an upper insulating layer comprised of a silicon nitride (SiN) layer 111 and a silicon dioxide (SiO2) layer 112 is formed on the upper wiring layer 110.
As explained above, in a dual-damascene multi-layered wiring structure, the via-conductor 109 through which the lower wiring layer 105 and the upper wiring layer 110 are electrically connected to each other is composed of the same material as a material of which the upper wiring layer 110 is composed. For instance, in the first example illustrated in FIG. 1A, both of the via-conductor 109 and the upper wiring layer 110 are composed of copper.
The above-mentioned dual-damascene multi-layered wiring structure is accompanied with a problem of void caused by the above-mentioned migration of copper. Examples of void are illustrated in FIGS. 1B, 1C and 1D.
FIG. 1B illustrates an example in which void 120B is observed almost at the center of the via-hole 108. The void 120B observed almost at the center of the via-hole 108 electrically insulates the lower wiring layer 105 and the upper wiring layer 110 from each other.
FIG. 1C illustrates an example in which void 120C is observed at a bottom of the via-hole 108. The void 120C observed at a bottom of the via-hole 108 electrically insulates the lower wiring layer 105 and the upper wiring layer 110 from each other, similarly to the void 120B illustrated in FIG. 1B.
FIG. 2 is a photograph of void generated at a bottom of a via-hole, taken through an electron-microscope.
FIG. 1D illustrates an example in which void 120D is observed at the side of the lower wiring layer 105 at a boundary between the via-conductor 109 and the lower wiring layer 105. Though the void 120D is not generated inside the via-hole 108 unlike the voids 120B and 120C illustrated in FIGS. 1B and 1C, the void 120D electrically insulates the lower wiring layer 105 and the upper wiring layer 110 from each other, similarly to the voids 120B and 120C illustrated in FIGS. 1B and 1C.
FIGS. 1A to 1C illustrate examples of voids observed in a multi-layered wiring structure which is a three-dimensional structure. Void is generated not only in a three-dimensional multi-layered wiring structure, but also in a two-dimensional planar structure.
FIG. 3 is a plan view illustrating an example of a copper wiring structure.
As illustrated in FIG. 3, a first wiring layer 121 having a first wiring width W1 and a second wiring layer 122 having a second wiring width W2 greater than the first wiring width W1 are electrically connected to each other. The first wiring layer 121 and the second wiring layer 122 are formed in a common layer, and have the same thickness as each other. The first wiring layer 121 and the second wiring layer 122 are composed of copper.
In the copper wiring structure illustrated in FIG. 3, if a volume of the second wiring layer 122 is significantly greater than a volume of the first wiring layer 121 (since the first wiring layer 121 and the second wiring layer 122 have the same thickness, “a volume” may be replaced with “an area”), copper is agglomerated inside the first wiring layer 121. As a result, a tensile stress 123 directing towards the second wiring layer 122 from the first wiring layer 121 is generated, and thus, the second wiring layer 122 is absorbed into the first wiring layer 121.
As a result, void 124 is generated at an end of the first wiring layer 121.
As explained so far, in both of a three-dimensional multi-layered wiring structure and a two-dimensional planar wiring structure both fabricated through a dual-damascene process, void is generated due to migration of copper of which a wiring layer is composed, and the thus generated void causes electrical insulation between wiring layers.
Thus, many wiring structures have been suggested so far to avoid void caused by copper migration.
As an example of such a wiring structure, FIGS. 4A and 4B illustrate a damascene wiring structure suggested in Japanese Unexamined Patent Publication No. 2001-298084 (A).
FIG. 4A is an upper plan view of the damascene wiring structure suggested in the above-mentioned Publication, and FIG. 4B is a cross-sectional view taken along the line 4B—4B in FIG. 4A.
The illustrated damascene wiring structure is comprised of a lower wiring layer 130, an interlayer insulating film 131 formed on the lower wiring layer 130, and an upper wiring layer. 132 (illustrated with a broken line) formed on the interlayer insulating film 131.
The interlayer insulating film 131 is formed at a surface thereof with a recess 131a, and further formed at a bottom of the recess 131a with a via-hole 133 reaching the lower wiring layer 130. The via-hole 133 has a diameter smaller than a width of the recess 131a. 
Around the via-hole 133 are formed four projections 134 upwardly projecting from a bottom of the recess 131a. The projections 134 are composed of the same material as a material of which the interlayer insulating film 131 is composed.
It is alleged in the above-mentioned Publication that the damascene wiring structure illustrated in FIGS. 4A and 4B can avoid defects caused by stress migration, typically such void generated in a copper wiring as mentioned above, even if a wiring had a long width, that is, a large volume.
However, the damascene wiring structure illustrated in FIGS. 4A and 4B is accompanied with a problem that it has to carry out complex photolithography and etching steps in order to form the projections 134, resulting in reduction in a fabrication yield.
In addition, since the projections 134 extend into the upper wiring layer 132 in the damascene wiring structure illustrated in FIGS. 4A and 4B, it would be quite difficult to estimate a resistance of the upper wiring layer 132, and to analyze current concentration occurring in the upper wiring layer 132.